As higher-density integration is realized for semiconductor chips such as a central processing unit (CPU) or an application-specific integrated circuit (ASIC), a connection-bump pitch has recently become smaller. It is desirable that a wiring board on which a semiconductor chip is mounted be able to cope with a small connection-bump pitch. Thus, instead of directly mounting a semiconductor chip on a package board composed of an existing ceramic substrate or an existing organic substrate, there have been cases where a silicon interposer is used between a semiconductor chip and a package board, the silicon interposer having advantages when performing fine patterning.
A silicon interposer has wiring layers on both surfaces, a semiconductor-chip mounting surface (a front surface) and a package-board connecting surface (a back surface), and silicon through vias are used to connect front-surface wiring and back-surface wiring. Note that, without forming silicon through vias and a back-surface wiring layer, a package board may be electrically connected to a semiconductor chip by wire bonding from a front surface of a silicon interposer.
There may be a case where it is desirable that wiring lines that transfer signals within a silicon interposer allow a plurality of signal transmission times to be made uniform like memory bus signals. This has been previously satisfied by performing meander processing in which, in an equal-length group in a silicon interposer, wiring lengths of wiring lines in the entire equal-length group are made to be equal to the wiring length of the longest wiring line in the equal-length group.
However, as wiring in a silicon interposer is made finer and comes to have higher density, it is more difficult to obtain a sufficiently large region for performing meander processing on a silicon interposer. Thus, a new wiring structure and a design method therefor have been desired that may make signal transmission times for a plurality of wiring lines be uniform even in the case of high-density wiring. The following documents are listed as examples of the related art, Japanese Laid-open Patent Publication No. 2003-152290, Japanese Laid-open Patent Publication No. 2004-031531, and Japanese Laid-open Patent Publication No. 2008-171950.